The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 1989
Filed:
May. 29, 1987
Morris D Ward, Garland, TX (US);
Kenneth L Williams, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
A cascadable first-in, first-out memory unit (11, 12, 13) has a load/unload control (152) for write-addressing and read-addressing selected memory locations within its memory array (82). A write pointer (110, 112, 120) keeps track of the number of write operations that have occurred in the selected memory unit, and a read pointer (130, 132, 142) does the same for the number of read operations. When the number of write operations performed since a last reset pulse (416) equals the number of memory locations in the memory array (82), write control passes to the next succeeding FIFO memory unit by a descending transition of an output control signal (444). Read control is passed to the subsequent FIFO by an ascending transition (470) of the same output control signal. Combination first load, master reset and output control circuitry (54-58, 192) is provided to select the first memory unit (11) for read and write operations, and to disable the outputs (18) of all of the FIFO memory units independent of the master reset signal (55).