Automatic cell-layout arranging method and apparatus for polycell logic

Abstract

In an automatic cell-layout arranging system for a polycell logic LSI, polycells are initially arranged in the form of cell arrays on a chip substrate. Connection paths for wiring lines among the polycells are then determined in accordance with cell-wiring requirements, so as to maximally satisfy a predetermined object function, thereby obtaining an LSI logic circuit capable of performing the desired function. A processor unit calculates a first number 'N' of wiring lines actually extending through each of the cell arrays, and a second number 'ml' representing an allowable number of through-lines for each cell array. Thereafter, this unit calculates a third number 'K' representing the difference 'ml-N' between the first and second numbers. When a certain cell array where the third number 'K' is less than zero is included in the cell arrays, the standard cells are rearranged on the chip substrate such that the third number 'K' is increased to zero or more than zero, thereby maximally eliminating the need to use through-cells for passing wiring lines through the cell arrays.