The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jun. 13, 1989
Filed:
Dec. 16, 1987
Howard L Tigelaar, Allen, TX (US);
Allan T Mitchell, Garland, TX (US);
Bert R Riemenschneider, Murphy, TX (US);
James L Paterson, Richardson, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
An X-cell EEPROM array includes a plurality of common source regions (50) that each border on four gate regions (46), both formed at a face of a semiconductor substrate (10). Each gate region (46) further adjoins a common drain region (52). Each drain region (52) is a common drain for two EEPROM select and memory transistors. A common erase region (54) is implanted into the semiconductor layer (10) in a position remote from the source regions (50) and the drain regions (52). Four floating gate electrodes (40) extend over tunnel windows (22) that are formed on the semiconductor layer (10) in positions adjacent a single erase region (54). An integral contact (64) is made through multilevel oxide (56, 58) from a metal erase line (70) to each erase region (54).