The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jun. 06, 1989

Filed:

Mar. 27, 1987
Applicant:
Inventors:

Alex E Henderson, El Granada, CA (US);

Frederick L Drain, So. San Francisco, CA (US);

Lawrence G Roberts, Woodside, CA (US);

Assignee:

NetExpress Systems, Inc., San Mateo, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06K / ;
U.S. Cl.
CPC ...
382 56 ; 358260 ;
Abstract

An apparatus for selecting a reference line for image data compression including a plurality of mutually connected reference selector chips for selecting a reference scan line from vertical mode coding of image data. The reference selector chips select a reference scan line from a plurality of preceding scan lines in exclusive or combination of the image data of each candidate reference scan line with the image data from the input scan line. The candidate reference scan line that has the lowest number of dissimilar bits is selected as the reference scan line. Each candidate reference scan line has associated therewith a register having bit positions arranged from the highest order bit position to a lowest order bit position for storing a binary sum of the number of dissimilar bits. When the sums are compared, the binary value and successive bit positions are compared from the highest order bit position to the lowest order bit position. When the binary value for a compared bit position of a register is greater than the binary value in the corresponding bit position of another register, each reference selector chip generates a losing signal for indicating that the register lost the arbitration. When the lowest order bit position of a register is not greater than the lowest order bit position of any other register and no losing signal was generated for the register, the associated chip generates a winning signal for indicating which candidate reference scan line had the least number of bits dissimilar to the corresponding bits in the input scan line. Each chip further includes a circuit for establishing a priority among the candidate reference scan lines so that two registers both having the smallest binary sum will not create a deadlock.


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