Timing signal generator for a video signal processor

Abstract

A timing signl generator for use in a multi-processor real-time digital video processing system. Each processor in the multiprocessing system is responsible for processing a selected portion of the video picture frame, as diesignated by the timing signal generator in each processor. The timing signals include a write signal instructing the receipt of the input picture block, an execution signal instructing the processing of the picture block, and an output command signal instructing the read out of the processed picture block. The timing signal generator is composed of row and column memory circuits which are respectively addressed by row and column address counters. The counters are caused to advance in response to indications that preselected coordinates in the picture frame have been reached. As inputs, the timing signal generator receives the pixel clock as well as horizontal and vertical sync signals, the former and latter of which are counted to keep track of the current coordinates. Outputs from the rwo and column memories are decoded to form the write, execute and output command signals.