The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 23, 1989
Filed:
Mar. 25, 1988
Edward F Culican, Sr, Hyde Park, NY (US);
John D Davis, Beacon, NY (US);
John F Ewen, Yorktown Heights, NY (US);
Scott A Mc Cabe, Highland, NY (US);
Joseph M Mosley, Boca Raton, FL (US);
Allan L Mullgrav, Jr, Wappingers Falls, NY (US);
Philip F Noto, Marlboro, NY (US);
Clarence I Peterson, Jr, Wappingers Falls, NY (US);
Philip E Pritzlaff, Jr, Highland, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A single logic gate array chip is disclosed having a first portion dedicated to the generation of one or more clock signals and the remaining portion occupied by logic circuits. The first portion uses the same gate array cell design as embodied in the logic circuits of the remaining portion. Both portions are powered by similar gate array metallization patterns, although some of the cells of the clock signal sources are disconnected from the normal chip powering busses and are powered instead by respective control signal generators. Each control signal represents the frequency difference between a given clock signal and a reference signal. The cells which are powered by a given control signal introduce a commensurate signal delay to drive the clock signal frequency into a predetermined relationship with the frequency of the reference signal.