Method of and circuit for generating bit-order modified binary signals

Abstract

A method of and a circuit for generating address signals, wherein a binary index signal and a binary base address signal are stored in index and address registers, respectively, whereupon the index signal and the base address signal are added together to produce an initial output address signal representative of the arithmetic sum of the index and base address signals during an initial cycle of signal generating operation. The initial output address signal is tentatively storing in the address register and is added to the index signal to produce an output address signal differing in bit pattern from the initial output address signal during the cycle of signal generating operation immediately subsequent to the initial cycle. This output signal is likewise tentatively storing in the signal register and thereafter the index signal from the index register and the output address signal produced during each of the successive cycles of signal generating operation are added together to produce another output address signal differing in bit pattern from each of the output address signals produced during the immediately preceding cycle of signal generating operation, wherein the arithmetic sum is produced by carrying out a forward arithmetic addition from the least significant bits forward or a reverse arithmetic addition from the most significant bits backward.