Branch and return on address instruction and methods and apparatus for

Abstract

A method of operating a digital data processor includes the supplying to the digital data processor of a branch and return on address (BAROA) instruction having an operation code field, a memory entry address field and a memory exit address field. This method also includes for such branch and return on address instruction the steps of loading the operation code field into an instruction register, loading the memory exit address field into an address register and loading the memory entry address field into a program counter. This method further includes storing the next sequential address following the address of the current BAROA instruction into a register stack, and then fetching from memory and executing a sequence of instructions starting with the instruction residing at the memory entry address provided by the branch and return on address instruction. The program counter is incremented each time an instruction is executed. In this manner, the program counter provides the memory addresses of the instructions to be fetched. This method further includes the steps of comparing the memory address in the program counter with the exit address in the address register and loading a return instruction operation code into the instruction register when the memory address in the program counter becomes equal to the exit address in the address register, such return instruction operation code, in turn, causing the address stored in the register stack to be loaded into the program counter.