The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 1989

Filed:

Sep. 29, 1987
Applicant:
Inventors:

Virgilio N Garcia, Melbourne Beach, FL (US);

Alan S Hearn, Dallas, TX (US);

Steven E Sparks, Garland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
307480 ; 307450 ; 307459 ; 307596 ; 307606 ; 357 16 ; 364900 ;
Abstract

A GaAs register for storing of digital data is configured with a plurality of 'D' type flip-flops having a data terminal and an enable terminal connected to an enabled GaAs clock circuit. The enabled GaAs clock circuit provides a load clock signal to enable the 'D' type flip-flops during the loading of data into the plurality of 'D' type flip-flops and to prohibit the loading of data without the load clock signal. The enabled GaAs clock circuit has 'D' type flip-flop, a clock input circuit and a combining circuit. The clock input circuit receives a clock signal and delays the clock signal. The 'D' type flip-flop loads the load enable signal with the rising edge of the clock signal and the delayed clock signal and the loaded enable signal are combined to obtained a combination signal which is used to load data into the plurality of 'D' type flip-flops in the register.


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