The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 16, 1989

Filed:

Apr. 11, 1986
Applicant:
Inventors:

Yoichi Kuroki, Kawasaki, JP;

Ruri Onoda, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01B / ;
U.S. Cl.
CPC ...
356401 ; 364559 ;
Abstract

An alignment device usable in the processes for manufacture of semiconductor integrated circuits, for bringing a mask and a semiconductor wafer into a predetermined positional relation by use of alignment marks, prior to effecting transfer of an integrated circuit pattern of the mask onto a photosensitive layer of the wafer. The alignment device is provided with a function of searching a mark signal included in a detection signal for the wafer, on the basis of the dimension of the alignment mark. By this, the alignment mark signal can be accurately detected irrespective of the fact that a noise component might be included in the detection signal for the wafer due to effects of the existence of the photosensitive layer or the like. In another aspect, the alignment device is operable in an operation mode including the mark signal searching step and in another operation mode not including the signal searching step. The selection of the operation mode is determined in accordance with the magnitude of the noise component included in the detection signal for the wafer, whereby an unpreferable decrease in the throughput is prevented. In a further aspect, signals from alignment marks of the mask and the wafer are processed in a parallel fashion whereby substantial reduction in the signal processing time is assured.


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