The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
May. 09, 1989
Filed:
Nov. 23, 1987
Michael J McNutt, El Toro, CA (US);
Ford Aerospace & Communications Corporation, Detroit, MI (US);
Abstract
A programmable voltage offset circuit (PVOC) (1) comprises a temporary latch memory (7); a latch disable circuit (5) which selects that PVOC (1) among several such circuits which may be simultaneously present on the same semiconductor chip; a resistor array (3); and a programmable nonvolatile memory (37). The desired voltage offsets V(OFFSET)s are temporarily produced in an iterative manner using the latch memory (7). Quasi-permanent voltage offsets V(OFFSET)s are then programmed using the nonvolatile memories (37), each of which typically comprises an EPROM (39). Application of an avalanche voltage V(STORE) to a PFET (43) portion of the EPROM (39) causes the PFET (43) to avalanche, thereby selectively programming the nonvolatile memory (37), depending upon the status of a signal supplied from the latch memory (7).