The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 09, 1989

Filed:

May. 02, 1988
Applicant:
Inventor:

Alexander J Yerman, Scotia, NY (US);

Assignee:

General Electric Company, Schenectady, NY (US);

Attorneys:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ;
U.S. Cl.
CPC ...
437-8 ; 437 51 ; 357 45 ; 364491 ;
Abstract

An additive process allowing discretionary interconnection of only the acceptable devices on a semiconductor wafer includes screen printing a polyimide layer over the wafer to form vias over all of the device contact pads on the wafer while coating the remainder of the wafer. The devices are then individually tested through the vias and, when a device is determined to be unacceptable according to predetermined specifications, the vias above that device are filled with polyimide. A layer of metal is next deposited over the entire wafer by evaporation and makes electrical contact with only the acceptable devices since the unacceptable devices have been blocked off. The metal layer is thereafter patterned to leave an interconnection pattern wherein only the acceptable devices on the wafer are electrically connected.


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