The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
May. 02, 1989

Filed:

Aug. 27, 1987
Applicant:
Inventors:

Richard J Pimpinella, Hampton, NJ (US);

John M Segelken, Morristown, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G02B / ; G02B / ;
U.S. Cl.
CPC ...
350 9620 ; 350 9617 ;
Abstract

The disclosed means for coupling an optical fiber and an opto-electronic device (e.g., LED, Laser, or photodetector) comprises a first body having two substantially parallel major surfaces, with a recessed portion (a 'well') formed in one surface, and a through-aperture extending from the other surface to the well. Conductive means extend from the former surface onto the bottom of the well, and the opto-electronic device is to be mounted in the well such that the device does not protrude above the plane of the associated surface, such that electrical contact is established between the device and the conductive means, and such that the active region of the device is centered upon the through-aperture. The first body is advantageously from a (100) Si wafer by means of standard Si processing techniques, including selective etching. The assembly can be mounted on a substrate, e.g., a Si wafer with appropriate metallization thereon, and the end of an optical fiber inserted into the through-aperture and secured to the first body. The assembly can be operated at relatively high speed, due to its relatively low parasitic capacitance and inductance, and can be mounted on the substrate in substantially the same way as IC chips are mounted, in close proximity to associated electrical components.


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