The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 25, 1989
Filed:
Jun. 24, 1988
Mitsuya Kawata, Yokohama, JP;
Fujitsu Limited, Kanagawa, JP;
Abstract
A semiconductor integrated circuit device has a normal mode and a test mode for testing a memory thereof, and comprises input/output buffer parts having input/output terminals, at least one gate array, at least one memory, a first interconnection for coupling the input/output buffer parts, the gate array and the memory and routed depending on a logic operation to be carried out by the semiconductor integrated circuit, and a second interconnection for coupling the input/output buffer parts, the gate array and the memory, where the second interconnection is fixed regardless of the logic operation to be carried out by the semiconductor integrated circuit. The input/output buffer parts comprise a first input/output part having a first terminal which is used in common as an input terminal of the first interconnection for receiving a normal input signal in the normal mode and an input terminal of the second interconnection for receiving a test signal in the test mode, and a second input/output part having a second terminal which is used in common as an output terminal of the first interconnection and an output terminal of the second interconnection.