The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 25, 1989

Filed:

Apr. 14, 1987
Applicant:
Inventor:

Thomas Hornak, Portola Valley, CA (US);

Assignee:

Hewlett-Packard Company, Palo Alto, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ; G11C / ;
U.S. Cl.
CPC ...
307353 ; 307267 ; 307606 ; 307605 ; 328151 ;
Abstract

A sample-and-hold circuit distinguished by its lack of a storage capacitor. The circuit includes a delay line and a signal following circuit coupled to the delay line which is synchronized with the delay line's propagation rate. In several embodiments of the invention a multi-tap delay line is used, and the signal following circuits variously include an electronic switch or linear interpolation circuits. In several other embodiments of this invention a gate of a FET is used as the delay line, and the signal following circuits include the drain and source of the FET. By substituting a delay line and signal following means for a storage capacitor, extremely fast sample-and-hold circuits may be obtained.


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