Integrated memory circuit having complementary bit line charging

Abstract

In a memory cell which is connected between two bit lines, information is stored after selection by causing a first bit line to convey a signal which is complementary to that on a second bit line. It is known, starting from a single data supply line which may convey either a high or a low signal, to provide a memory circuit per column with inverting means so as to be able to charge both bit lines complementarily. Here, this complementary charging is done by connecting, upon selection, the first bit line to the data supply line and connecting a transistor with its main electrodes between ground and the second bit line, which transistor receives the data at its control electrode. This transistor then constitutes, with the bit line load, an inverter. Lay-out aspects relate to the common use of substrate area of two adjacent columns and the common use of a contact in the shown circuit arrangement.