The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 18, 1989
Filed:
Jun. 29, 1988
Ikuo J Sanwo, San Marcos, CA (US);
James A Donahue, San Diego, CA (US);
Donald G Tipon, San Diego, CA (US);
NCR Corporation, Dayton, OH (US);
Abstract
A MOS circuit for trimming a digital pulse signal by delaying the rising edge of the pulse signal for a predetermined period of time and passing the falling edge without delay. The circuit includes two MOS output transistors and a signal buffer. The signal buffer has a number of stages for delaying the pulse signal, with the number chosen to control the delay in the rising edge of the pulse signal. One of the output transistors receives the pulse signal at its drain and is enabled by the delayed pulse signal from the signal buffer to pass the pulse signal after the predetermined period of time to its source at the output of the circuit, so that the rising edge is delayed, but the falling edge is not. The other output transistor is enabled to ground the output of the circuit after the falling edge of the pulse signal. A self-booting circuit drives the gate of the one output transistor to assure that the voltage level of the trimmed signal will not be reduced by dissipation across the transistor.