The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Apr. 11, 1989

Filed:

May. 11, 1988
Applicant:
Inventors:

Kazutoshi Shimizume, Kanagawa, JP;

Mutsumi Kimura, Kanagawa, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K / ;
U.S. Cl.
CPC ...
375 81 ; 331 14 ; 328155 ; 360 43 ;
Abstract

A digital phase locked loop (PLL) circuit having an input terminal to which an input digital signal is supplied, a counter for counting a reference clock, a digital phase comparator for comparing the phases of the input digital signal and the output of the counter, a digital low-pass filter supplied with the output of the digital phase comparator, a correction control signal generating circuit and a control circuit, whereby the quantization error is reduced to improve the follow-up characteristic of the digital PLL circuit. Also, the digital PLL circuit contains no residual phase error and this highly-stable digital PLL circuit is arranged so as not to respond to a high frequency fluctuation component such as a peak shift.


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