The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1989
Filed:
Mar. 09, 1987
Applicant:
Inventors:
Takashi Makino, Tokyo, JP;
Shuji Asami, Yokohama, JP;
Assignee:
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H03K / ;
U.S. Cl.
CPC ...
307603 ; 307606 ; 307605 ; 307594 ; 307595 ; 307452 ; 328 55 ;
Abstract
A delay circuit comprising a plurality of clocked inverters coupled cascade form. Each clocked inverter includes a plurality of MOS FETs. The circuit further comprises delay time-controlling MOS FETs connected in parallel to the MOS FETs of the clocked inverters, which are controlled by clock signals. When the delay time-controlling MOS FETs are turned on, the clocked inverters function as ordinary inverters. Conversely, when the delay time-controlling MOS FETs are turned off, the clocked inverters perform their own functions. Hence, one of two different delay times can be selected.