The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1989
Filed:
Sep. 19, 1985
Hung-Cheng Hsieh, San Jose, CA (US);
Xilinx, Incorporated, San Jose, CA (US);
Abstract
A TTL/CMOS compatible input buffer includes an input inverter and a reference voltage generator. In the TTL mode, the reference voltage generator supplies a reference voltage to the source of the P-channel transistor in the inverter having a magnitude which forces the trigger point of the input inverter to assume a preselected value. Typically the preselected value is selected to be 1.4 volts in order to maximize the input noise margins. A second stage input inverter introduces hysteresis to improve the noise immunity of the system. The reference voltage generator includes an operational amplifier connected to a voltage divider network. In the CMOS mode, the reference voltage generator is disabled and a voltage equal to power supply voltage is provided to the input inverter. As a result, the trigger point of input inverter is higher than 1.4 volts which provides a larger input noise margin. The voltage divider network and the operational amplifier are powered down so that no DC power is consumed.