The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 11, 1989
Filed:
Sep. 08, 1987
Applicant:
Inventors:
Hendrikus J Veendrick, Eindhoven, NL;
Cornelis G Van Der Sanden, Eindhoven, NL;
Arie Slob, Eindhoven, NL;
Assignee:
U.S. Philips Corp., New York, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K / ; H03K / ; H03K / ; H01L / ;
U.S. Cl.
CPC ...
3072962 ; 307592 ;
Abstract
In CMOS integrated circuits, 'latch-up' problems may arise if no special steps are taken. One way to counteract a 'latch-up' state is to apply a substrate bias voltage. In an integrated circuit, an externally-clocked substrate bias voltage pump and a stand-by bias voltage generator are provided, the latter not being switched on until the substrate bias voltage becomes less negative than, for example, -2V. As a result, the integrated circuit becomes less sensitive to 'latch-up', especially during measuring and testing procedures, in which no external clock signal is supplied.