Nonvolatile semiconductor memory device with readout test circuitry

Abstract

A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.