The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 04, 1989
Filed:
Apr. 05, 1985
Applicant:
Inventors:
Andrew T Jennings, West Chester, PA (US);
Joseph S Schibinger, Phoenixville, PA (US);
Ronald J Kalemba, Berwyn, PA (US);
Assignee:
Unisys Corporation, Blue Bell, PA (US);
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
364200 ;
Abstract
An array of various types of processors for the purpose of simulating computer functions for large computer systems. These functions may vary from simple AND, OR and other functions to large arithmetic logic units and even random access memories. The simulation array is a tree-type array where the leaves of the tree are the actual logic simulation processors with the other processors serving as nodes which route change of value notices among the various logic simulation processors.