Low jitter phase-locked loop

Abstract

In the preferred embodiment of the invention the jitter in the output signal of a phase-lock loop is minimized by driving a voltage controlled oscillator (VCO) with the average voltage level that appears across a capacitor. The voltage level is maintained by selectively pumping a charge into the capacitor as a function of the deviation of the output signal, from the VCO, from a desired output in a first direction. The charge on the capacitor is allowed to partially bleed off to ground through a variable resistance such that the charge on the capacitor is maintained at levels that cause a slight phase lag in the operation of the voltage controlled oscillator. The phase-locked loop more specifically utilizes an error detector for receiving an incoming digital signal to which the phase-locked loop is to lock and a reference signal corresponding to a divided output signal from the phase-locked loop. The error detector provides signals indicative of the magnitude and the direction of the difference between the incoming digital signal and the reference signal. The difference signals are coupled to a pulse driver circuit for providing pulse charges as a function of the difference signals. A low pass filter having a capacitor receives the pulse charges for charging the capacitor. The low pass filter also incldues means for controllably discharging the capacitor. A voltage controlled oscillator provides an output signal having a phase that is a function of the magnitude of the charge on the capacitor. A divider circuit divides the output signal by selected integers to provide to the error detector the reference signal.