Method of manufacturing an integrated cmos of ordinary logic circuit and

Abstract

A method of manufacturing a semiconductor device having a high voltage CMOS unit for an ordinary logic operation and a MOS unit which are provided in a single semiconductor substrate of a first conduction type. The method includes the steps of performing an element region making process for making a well of a second conduction type in the substrate, performing a process for providing field-effect transistors having channels of mutually different conduction types in the substrate and the well, and then performing a process for providing electrode wiring layers. Finally, a process is performed for providing a first impurity region having a particular conduction type and serving as a channel stopper of the CMOS unit and a second impurity region having the conduction type of the first impurity region and serving as an offset low-resistance layer of the high voltage MOS unit.