Digital correlator

Abstract

A digital correlator for determining the offset time between two random signals offset in time with respect to each other includes an analog signal processing arrangement and a digital signal processing unit. The analog signal processing arrangement generates by binarizing and periodic sampling of the random signals and their derivatives binary signals, each of which represents the polarity of one of the random signals or the derivative of a random signal at the sampling instants. The digital signal processing unit includes two delay circuits, each of which imparts to one of the binary signals a delay of an adjustable multiple of the sampling period. Each delay circuit is formed by a write-read memory into the memory cells of which the consecutive bits of the binary signal to be delayed are written at the sampling rate under consecutive write memory addresses and out of the memory cells of which the stored bits are read at the sampling rate under consecutive read memory addresses differing from the write memory addresses by an adjustable address difference. Furthermore, the digital signal processing unit comprises two correlation units, each of which receives a delayed binary signal, an undelayed binary signal and a derivative binary signal corresponding to the derivative of the undelayed binary signal. Each correlation unit counts the sampling periods which are contained in an averaging time interval and in which a quantity calculated from the binary signals supplied assumes a positive numerical value or a negative numerical value. A computing and control circuit calculates from the two counts estimated values of correlation coefficients and their derivatives and controls the adjustable address difference in each delay circuit in dependence upon said estimated values so that the delay time is kept equal to the offset time.