Clamp circuit for a solid-state image device

Abstract

A clamp circuit for a solid-state imaging device which includes a clamp circuit for clamping at a black reference voltage level a video signal at a signal level which is obtained when an optical black portion formed on the solid-state imaging device is read, a detection circuit for detecting the increase in voltage of the optical black portion, a circuit for interrupting vertical transfer clock signals of the solid-state imaging device during at least one horizontal line interval during a vertical blanking period, and a switching circuit which when the detection means detects an abnormal voltage of the optical black portion, supplies a clamp pulse which is generated with a timing associated with the interruption of the transfer clock signals instead of the clamp pulse of the optical black portion. A circuit for detecting a voltage abnormality of the optical black portion provided to an imaging surface, and a circuit for interrupting the vertical transfer clock signals during at least one horizontal line period in the vertical blanking period are connected in the clamp circuit of the solid-state imaging device and when an abnormally high voltage is generated at the optical black portion, a video signal portion which is cleared upon interruption of the transfer clock signals is overincidence state, is prevented.