The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 28, 1989

Filed:

May. 04, 1987
Applicant:
Inventor:

Engel Roza, Eindhoven, NL;

Assignee:

U.S. Philips Corporation, New York, NY (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03F / ;
U.S. Cl.
CPC ...
330149 ; 330-9 ;
Abstract

An amplifier arrangement for reducing an unwanted d.c. offset of an amplitude-varying input signal, has a threshold circuit (A.sub.3, B.sub.3) and an amplifier stage (A.sub.1, B.sub.1) coupled thereto, which threshold circuit (A.sub.3, B.sub.3) is provided with a bistable trigger circuit (A.sub.4, B.sub.4). This bistable trigger circuit (A.sub.4, B.sub.4) reduces the d.c. level of the input signal or output signal of the amplifier stage (A.sub.1, B.sub.1) in a steplike manner when this d.c. level increases. The bistable trigger circuit (A.sub.4, B.sub.4) has a hysteresis which is larger than the maximum amplitude variation of the input signal as a result of the desired signal component, so that a linear amplification of this desired signal component is possible and, in the case of a non-varying d.c. level, variations of the input signal due to the desired signal component cannot give rise to a d.c. reduction. This amplifier arrangement may be used in a phase-locked loop of a directly mixing synchronous AM receiver, which phase-locked loop is used for generating a synchronous local carrier in order to increase the input dynamic range of the receiver.


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