The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 21, 1989
Filed:
Aug. 05, 1987
Pham N Tung, Paris, FR;
Thomson-CSF, Paris, FR;
Abstract
An active load in an integrated logic circuit of the Direct Coupled FET Logic (DCFL type) in which the active load has a negative threshold voltage and the transistors have a positive threshold voltage. The active load is a transistor, the gate metallization of which is combined with the source metallization. If the active load delivers an excessive current, this current can be adjusted by adding at least one second gate which has a positive threshold voltage and which is in electrical contact with the first gate with a negative threshold voltage. The appropriate threshold voltages are obtained by bombarding the corresponding gate regions. The transistors of the integrated circuit are obtained during the manufacture of the second gate.