The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 1989

Filed:

Jul. 10, 1987
Applicant:
Inventors:

Masatoshi Kimura, Ome, JP;

Takeaki Okabe, Tokyo, JP;

Isao Yoshida, Tokyo, JP;

Kouzou Sakamoto, Nerima, JP;

Kazuo Hoya, Takasaki, JP;

Kouichiro Satonaka, Maebashi, JP;

Toyomasa Koda, Takasaki, JP;

Shigeo Ohtaka, Takasaki, JP;

Assignee:

Hitachi, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437 59 ; 437 31 ; 437 61 ; 437 97 ;
Abstract

A method of fabricating semiconductor devices which include vertical elements and control elements. A well is formed by etching in a semiconductor substrate of a first conductivity type, and a first epitaxial layer having a second conductivity type opposite to the first conductivity type is epitaxially grown, followed by etching and/or grinding and/or polishing to fill said well. Further, a second epitaxial layer of the first conductivity type is epitaxially grown on the substrate and on the first epitaxial layer, and an impurity-doped layer of the second conductivity type for isolation is formed in the second epitaxial layer to penetrate therethrough. A first element is formed in the second epitaxial layer in a portion that corresponds to the well, and a second element having a vertical structure and having a current capability higher than that of the first element is formed except a portion of the second epitaxial layer that corresponds to the well.


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