The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 21, 1989

Filed:

Oct. 22, 1987
Applicant:
Inventors:

Kazuhiko Inoue, Yokohama, JP;

Yutaka Tomisawa, Yokohama, JP;

Assignee:

Kabushiki Kaisha Toshiba, Kawasaki, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437022 ; 437027 ; 437061 ; 437904 ;
Abstract

A GaAs planar diode includes an N type GaAs substrate having an N.sup.+ GaAs layer on which an N.sup.- GaAs layer is formed. A first impurity layer of the N.sup.+ type is formed on the N.sup.31 GaAs layer. A second impurity layer of a p.sup.+ type is formed on the first impurity layer, wherein a p-n junction is formed between the first and second impurity layers. A semi-insulation region, for encompassing a predetermined area of the p-n junction of the first and second impurity layers, is formed in the substrate. The depth of the semi-insulation region in the substrate is deeper than the total depth of the first and second impurity layers, so that the semi-insulation region serves as an element isolation region of the p-n junction of the first and second impurity layers.


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