Data processing apparatus for processing list vector instructions

Abstract

List operation on a vector in which the number of an element of a vector operand is represented by an element of another vector operand is to be performed with a general-purpose computer system having no vector registers. List vector elements are read out from a memory by adding at addresses determined sequentially by adding by adding values of a request vector increment register to a list vector address. A value resulting from the bit shift of the element is stored in a second operand increment register. A second vector element is read out from the memory at the address corresponding to a value resulting from addition of the content of the second operand increment register to the second operand initial address register, the element being then stored at the memory location of the address given by a value resulting from the addition of the value of the first operand vector increment register to the first operand address.