The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 14, 1989

Filed:

Dec. 17, 1987
Applicant:
Inventor:

David Bingham, San Jose, CA (US);

Assignee:

Maxim Integrated Products, Sunnyvale, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H03K / ;
U.S. Cl.
CPC ...
357 35 ; 357 36 ; 357 43 ; 307303 ;
Abstract

A bipolar lateral pass-transistor is disclosed for use in MOS integrated circuits. The transistor includes a semiconductor substrate of a first conductivity type covered by an epitaxial layer, a first region of a second conductivity type disposed in the epitaxial layer at a first doping level to a depth of less than the depth of said epitaxial layer, a second region of said conductivity type spaced apart from and surrounding said first region and extending approximately the entire depth of said epitaxial layer having a doping level less than the first doping level and a third region of said second conductivity type spaced apart from and surrounding said second region and extending approximately the entire depth of said epitaxial layer having said first doping level at the surface of said epitaxial layer and said second doping level extending approximately to the bottom of said epitaxial layer. In another aspect of the present invention the bipolar lateral pass-transistor is connected to a voltage source and MOS devices also disposed on the surface of the semiconductor substrate are powered by a voltage which is less than the voltage applied to the lateral pass-transistor, in order to prevent desirable forward biasing of parasitic PN junctions.


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