Interconnect circuit

Abstract

An interconnect circuit for use in a computer system employing horizontal architecture and having multiple resources of which the use must be scheduled in an optimum manner. The interconnect circuit reduces scheduling to a mechanical task by providing multi-word storage capability at each of a plurality of cross-points connected in data flow paths between the computer resources. At each cross-point of the interconnect circuit, data may be written into a selected location and retrieved from a selected location. Writing may be accomplished by an insertion operation in which already stored data is shifted to vacate the location selected for writing. Likewise, reading can be accompanied by a purge operation in which already stored data are shifted into the location from which a data word is purged. In this manner each cross-point can function as a time delay in a data path, to facilitate scheduling of resource usage.