The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 1989
Filed:
Jan. 21, 1988
Harold W Dozier, Carrollton, TX (US);
Thomas M Jones, Dallas, TX (US);
Steven J Wallach, Dallas, TX (US);
Jeffrey H Gruger, Dallas, TX (US);
Convex Computer Corporation, Richardson, TX (US);
Abstract
An operand processing unit (10) carries out processing of operands in a computer. The unit (10) includes a plurality of operation circuits (12, 14, 16, 18, 20). A source bus (22) provides one operand per clock cycle to the operation circuits (12, 14, 16, 18, 20). A destination bus (24) receives one resultant per clock cycle from the operation circuits (12, 14, 16, 18, 20). Within each operation circuit there is provided an operand processing circuit (80) which performs a selected function with the received operands. These functions include, for example, multiplication, division, addition, subtraction, logical AND, and shift. Logical circuitry provides a priority assignment to the operation circuits (12, 14, 16, 18, 20) for sequencing the loading of operands into the highest priority operation circuit (12, 14, 16, 18, 20) which is not busy processing operands within its corresponding operand processing circuit (80). The operand processing unit (10) provides concurrent processing of operands to enhance processing speed. The operands and resultants are handled in a manner such that there is a uniform and sequential flow of operands from a source, such as main memory, and a uniform and sequential delivery of resultants to a destination, such as a memory or input/output device.