The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 28, 1989
Filed:
Aug. 21, 1987
Nobutake Matsumura, Yokohama, JP;
Shinji Sato, Yokohama, JP;
Fujitsu Limited, Kawasaki, JP;
Abstract
A gate array LSI includes a basic cell array region on which internal cell arrays are arranged, and a peripheral circuit region, arranged on the periphery of the basic cell array region. The peripheral circuit region includes input/output cell regions, for constructing an input buffer circuit and part of an output buffer circuit, and a general purpose cell array region, for constructing the remaining part of the output buffer circuit. When the output buffer circuit is not constructed, the general purpose cell array region is used for constructing various other desired circuits.
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile