The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 21, 1989

Filed:

Jun. 13, 1986
Applicant:
Inventor:

Jack Sacks, Thousand Oaks, CA (US);

Assignee:

Multilink Group, Calabasas, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04N / ;
U.S. Cl.
CPC ...
358141 ; 358142 ; 358133 ;
Abstract

A decoder for use in a multiplexing system wherein the adjacent frame lines of a first program are summed and differenced, and the sum signal and time-compressed difference signal of each line pair is transmitted during the period allotted for transmission of a single line, thereby transmitting data for two lines in the time allotted for a single line. The decoder avoids a need for complex digital wall filters at the input by sampling the timed-compressed difference signals at a non-unity multiple of the rate used for sampling the sum signals. The multiple is sufficiently fast to enable the standard 'front-end' low pass filter of the decoder to function as an interpolation filter, eliminating the artifacts which would otherwise require the use of the complex filter. The disclosed decoder additionally includes a first memory-sharing arrangement wherein memory addresses are accessed during each operating cycle in a manner which permits data to be written into memory prior to the complete reading out of data from the previous operating cycle. A second memory-sharing arrangement is included wherein memory addresses are accessed during each operating cycle in a manner which permits data to be read out of the memory prior to the complete writing of data for that operating cycle, enabling re-use of certain memory addresses during the operating cycle.


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