The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 21, 1989
Filed:
Aug. 11, 1986
Applicant:
Inventors:
Josef Winnerl, Landshut, DE;
Dezso Takacs, Munich, DE;
Assignee:
Siemens Aktiengesellschaft, Berlin and Munich, DE;
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ; H01L / ; H01L / ;
U.S. Cl.
CPC ...
357 42 ; 357 15 ; 357 231 ; 357 67 ;
Abstract
An integrated circuit in complementary circuit technology comprising a substrate bias voltage generator which applies a negative (positive) substrate bias voltage to the p(n) substrate in which n(p) tubs are inserted. The source regions of the n(p)-channel FETs arranged in the substrate lie at ground potential. In order to avoid 'latch-up' effects, an output of the substrate bias voltage generator is connected via a Schottky diode to a circuit point that lies at ground potential.
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Winnerl, Josef. (1989). Integrated circuit in complementary circuit technology comprising a (U.S. Patent No. 4807010). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/4807010
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