Method of manufacturing bi-cmos semiconductor ic devices using dopant

Abstract

The invention relates to a method of manufacturing a Bi-CMOS semiconductor IC device in which the bipolar transistor structure contained therein has a flat PN plane junction between its base and emitter regions, said device having improved breakdown voltage characteristics. The improved method involves preparing a silicon substrate having a P-type base region formed in an N-type collector region, forming a thick silicon oxide layer over the suface of a bipolar transistor region on said substrate, selectively removing the silicon oxide layer to form a first window exposing a part of the collector region and a second window exposing a part of the base region, diffusing phosporus atoms into the base region and collector region through said first and second windows to form an emitter region in the base region and a collector contact in the collector region, subjecting the structure thus-obtained to an oxidation process in a wet oxygen atmosphere at a temperature of 940.degree. C..+-. 20.degree. C. to form a thin silicon oxide layer in the windows, whereby the thin oxide layer on the emitter region invades the emitter region to accomodate the phosphorus atoms, selectively removing a portion of the thin oxide film to form a third window, thereby exposing a surface of the emitter region and subjecting the structure thus-obtained to an impurity drive-in process to rediffuse the phosphorus atoms contained in the remaining thin oxide film into the emitter region, whereby the PN junction plane between the base and emitter regions is flattened. Other variations of this general method are disclosed.