Serial first-in-first-out (fifo) memory and method for clocking the same

Abstract

A delay line digital memory is organized into n signal branches (z.sub.1 . . . z.sub.n), each with m cells which form a serial data or signal flow path. Each cell is comprised of a transfer transistor t with a subsequently following level restorer, regenerator, or buffer circuit p which, however, is omitted in the last cell. Furthermore, n clock signals (s.sub.l . . . s.sub.n) are provided whose frequency (or repetition rate) equals one n-th of the data rate of the digital input signals, and whose effective pulses follow each other in temporal serial succession within one period of the data rate. Clocking (or activation) by clock signals (s.sub.1 . . . s.sub.n) is chosen so that in the first signal branch (z.sub.1) the first transistor is fed with the last clock signal (s.sub.n); in the second signal branch, the first transistor is fed with the next to last clock signal (s.sub.n-1); in the next to last signal branch (z.sub.n-1), the first transistor is fed with the second clock signal (s.sub.2); and in the 1st signal branch (z.sub.n) the first transistor is fed with the first clock signal (s.sub.1) at its gate. The remaining transistors of each signal branch are then fed in the sense of a descending clock-signal numbering order. Both the inputs and outputs of the signal branches are assembled or led together to either the signal input (s.sub.e) or the signal output (s.sub.a). This arrangement results in a considerable saving of space in the case of a monolithic integration compared to the cases in which shift registers or dynamic random access memories (DRAMs) are employed. The effective length of the storage time can be reduced in increments corresponding to the magnitude of the period of the data rate of the input signal.