The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 31, 1989

Filed:

Feb. 05, 1987
Applicant:
Inventors:

Koyu Yamanoi, Tokyo, JP;

Yoshio Yoshizakiya, Tokyo, JP;

Masayoshi Dehara, Tokyo, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F / ;
U.S. Cl.
CPC ...
371 27 ; 371 28 ;
Abstract

A test signal generating circuit for generating a test signal for testing logic circuits comprises four delay units each including a setting circuitry for setting a delay time, a gate and a counter for counting clock pulses in number corresponding to the delay time placed in the setting circuitry. The output signals of two delay units are applied to a flip-flop as set input signals, while the output signals of the other two delay units are applied to the flip-flop as reset input signals, whereby the timing and/or waveform of the test signal outputted by the flip-flop is varied in dependence on the values placed in the setting circuitries.


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