Logic circuit

Abstract

A logic circuit which can easily perform a logical function test is disclosed. A first type of the logic circuit comprises a combinational circuit having a plurality of internal nodes, node data latch circuits respectively connected to the preselected internal nodes for latching their logical states, and readout means for reading data latched in the latch circuits by using a data transfer clock. Further, there may be adopted implementation such that the node data latch circuit functions to allow a predetermined node to be placed in the logical state latched in the node data latch circuit. Thus, this first type of the logic circuit makes it possible to monitor even logical states of internal nodes of the combinational circuit. A second type of the logic circuit comprises a combinational circuits, a plurality of memory means, designation means e.g. a flip-flops provided per each memory means for designating whether an access to the memory means is enabled or not, access means for providing an access to the memory means designated by the designation means, and means for setting designation data to the designation means. Further, there may be provided an address decoder for decoding addresses assigned to the respective designation means. Thus, the second type of the logic circuit can implement a logical function test with less additional circuitry and wiring and in a simplified control mode. In addition, the combination of the first and second types of the logic circuits is also possible.