The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 31, 1989
Filed:
Jul. 06, 1987
International Business Machines Corp., Armonk, NY (US);
Abstract
An integrated (silicon based) packaging/wiring structure provides for VLSI chips 4 to be placed within openings of somewhat larger size in a semiconductor interconnection wafer (IW, 2) supported by a carrier 1. The interconnection wafer 2 includes multilevel (ML) wiring planes and incorporated circuit components integrated in a less demanding technology as compared to the VLSI chips 4. Silicon contact chips 5 with conductive surface layers 22, 23 placed over the chip/IW plane provide for the required interconnections by means of needle-like structures 24 inserted in corresponding via holes. The needles are better suited to withstand shear strain than are conventional C-4 (Controlled Collapse Chip Connection) joints. Consequently a much higher number of chip pads can be provided. Power supply is effected via rather large-dimensioned conductive planes, e.g. in the form of Cu rails 20, running within the carrier 1 and surfacing stud-like (at 21) in the peripheral region of said openings in the interconnection wafer 2 for further distribution via the contact chip 5. The wiring system can be supplemented, if required, with an additional wiring wafer 6.