Velocity error correcting circuit for time base error corrector

Abstract

A main memory stores a signal reproduced from a recording medium with a time base error, and a read clock generator and phase modulator generates a read clock signal of variable phase for reading out the signal from the main memory. A velocity compensating circuit generates first discrete signals representative of the velocity error of the reproduced signal at designated sample points of a current field and second discrete signals representative of a velocity error of the reproduced signal at sample points of a previous field respectively corresponding to the designated points and interleaves the first and second discrete signals to produce a combined signal having a sampling frequency greater than that of either the first or second discrete signals. The combined signal constitutes a nonlinear approximation of the time base error, and the read clock generator and phase modulator is responsive to the combined signal for controlling the readout of the reproduced signal from the main memory in such a manner as substantially to eliminate the time base error.