Semiconductor memory device with reset signal generating circuit

Abstract

A semiconductor memory device includes a reset circuit for equalizing potentials of a pair of signal lines for transferring a complementary signal, and a clock generating circuit generating a first clock signal and a second clock signal at a time different from the generation of the first clock. A logical OR gate circuit generates a reset signal based on the first and second clock signals. When the pulse width of an active low chip selection signal is shorter than a predetermined time period, the pulse width of the reset signal is made longer than that generated when the pulse width of the signal is longer than the predetermined time period. As a result, the potentials of a pair of complementary bit lines connected to each cell in the memory cell array can be reliably reset, and the delay time in the access operation can be reduced.