The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 24, 1989
Filed:
Apr. 19, 1988
Masakazu Kakumu, Yokohama, JP;
Tetsuya Asami, Yokohama, JP;
Kabushiki Kaisha Toshiba, Kawasaki, JP;
Abstract
A method of manufacturing semiconductor devices according to the present invention includes the steps of forming an element isolation region on the main surface of a semiconductor substrate of a first conductivity type, forming a high impurity concentration layer of a second conductivity type in the surface area of a portion of the semiconductor substrate defined by the element isolation region, and forming a first insulation film on the entire surface of the resultant semiconductor structure. Thereafter, a contact hole is formed in the first insulation film which is formed on the high impurity concentration layer, a semiconductor layer containing an impurity of the same conductivity type as the high impurity concentration layer is formed on the first insulation film, and a second insulation film is formed on the semiconductor layer. After this, a planarization film is formed on the entire surface of the second insulation film and is then selectively removed by anisotropic etching, to leave part of the planarization film filling the contact hole. Then, the portion of the planarization film exposed by the anisotropic etching is removed, a metal layer is formed on the entire surface of the resultant semiconductor structure, and the metal layer and semiconductor layer are patterned to form a laminated structure of a wiring layer.