The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 17, 1989
Filed:
Apr. 28, 1986
Sheldon Pearlman, Stanford, CT (US);
Anatoly Fridland, Shelton, CT (US);
Gunther J Martin, Ridgefield, CT (US);
Kidde, Inc., Westlake, OH (US);
Abstract
A system and process for receiving phase-coherent FSK signals having data and clock components which includes a plurality of subsystems and a means for carrying data among the subsystems. At least two of the subsystems are able to communicate by means of a transmitter in one of them and a receiver in the other. The receiver includes a demodulator for separating the data and clock components of the encoded phase-coherent FSK signals. The clock demodulator includes a first transition detector and a 90-degree phase shift circuit which both receive the encoded signal. A second transition detector receives the output of the phase shift or phase delay circuit. An OR gate receives the output of the first and second transition detectors to produce a four times clock signal. The data component of the phase-coherent FSK signal is recovered by either of two alternate circuits. The first circuit uses a shift register which examines at least four samples of data in conjunction with a pair of exclusive OR gates, a NOR gate, and a flip-flop. An alternate data component demodulator includes a first 90-degree phase delay circuit and an inverter both receiving the encoded data and transmitting it to a first exclusive OR gate. A second 90-degree phase delay circuit receives the output of the first exclusive OR gate. A second exclusive OR gate receives the outputs of both the second phase delay circuit and the first exclusive OR gate.