Encoding or decoding circuit for time division multiplex and

Abstract

A circuit includes shift registers (SR1, SR2, SR3) having different write and read rates under the control of clock pulses of different frequencies so that they form part of a signal compression or signal expansion circuit for encoding from simultaneous signals to the time division multiplex signal and for decoding from the time division multiplex signal to the simultaneous signals, respectively. The circuit is an integrated circuit (IC) having shift registers (SR1, SR2, SR3) suitable for both series-in, parallel-out and parallel-in, series-out operation. The shift register (SR1) with the greatest number of register stages is coupled to parallel connections of at least two further shift registers (SR2, SR3) via a through-connection circuit SC1 for a parallel bi-directional connection of the register stages. The series inputs and series outputs of at least the three shift registers are each coupled to a connection terminal of the integrated circuit (IC).