Real-time video signal processing device capable of typically executing

Abstract

In a real-time video signal processor for processing an input digital video signal divisible into a succession of principal blocks each of which has at least one scanning line and a time duration shorter than a frame period, each principal block is divided into at least two partial blocks with each scanning line divided into the respective partial blocks. A plurality of signal processing modules are assigned with the respective partial blocks of each principal block, respectively. Responsive to the input digital video signal and an additional digital video signal, the signal processing modules process the respective partial blocks of each principal block into processed signals during the time duration, respectively. Each processed signal comprises a first partial signal used as an output signal of the processor and a second partial signal. A delaying circuit delays the second partial signals derived from the signal processing modules into a delayed signal having a delay equal to a difference between the frame period and the time duration. The delayed signal is used as the additional signal. A plurality of the real-time video signal processors may be connected in cascade to each other. Two memory units may be used instead of the delaying circuit. Readout operation of each principal block from the memory units is controlled by control signals produced by a control signal producing circuit. Principal blocks read out of the memory units are supplied to the signal processing modules.