The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 10, 1989

Filed:

Oct. 24, 1986
Applicant:
Inventors:

Douglas P Verret, Sugarland, TX (US);

Michael C Smayling, Freising, DE;

Abnash C Sachdeva, Houston, TX (US);

Stephen A Keller, Sugarland, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L / ; H01L / ;
U.S. Cl.
CPC ...
437034 ; 357 34 ; 357 42 ; 357 91 ; 437 31 ; 437 54 ; 437 57 ;
Abstract

A method of making a merged bipolar and field effect semiconductor transistors on a semiconductor substrate by forming a diffused buried DUF collector region of a second conductivity type in the substrate, and growing an impurity doped epitaxial layer of silicon of the second conductivity type over the substrate. Once the epitaxial layer is grown, a plurality of isolation regions are formed in this layer. A bipolar transistor is formed over the DUF region in a bipolar isolation region and a field effect transistor formed in the second isolation region. Contacts and interconnects are deposited and patterned.


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